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<a href="#groups">API Reference</a>  </div>
  <div class="headertitle">
<div class="title">GPIO (General Purpose Input Output)</div>  </div>
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<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>The GPIO driver provides an API to configure and access device Input/Output pins. </p>
<p>The functions and other declarations used in this driver are in cy_gpio.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.</p>
<p>IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and their variants.</p>
<p>Initialization can be performed either at the port level or by configuring the individual pins. For efficient use of code space, port configuration should be used in the field. Refer to the product device header files for the list of supported ports and pins.</p>
<p>A port is represented by <a class="el" href="struct_g_p_i_o___p_r_t___type.html" title="The struct type definition for the hardware register set contained in the block.  The address of a va...">GPIO_PRT_Type</a> and a pin is represented by a number 0 to 7.</p>
<p>For PSoC 64 devices the the un-intended protected pins (due to constrain on PPU configuration) are modified using PRA driver. But the GPIO diver does not modify the intended protected pins .</p>
<ul>
<li>Single pin configuration is performed by using <a class="el" href="group__group__gpio__functions__init.html#gaf57c501727276013d3e8974a9fb7d0a7">Cy_GPIO_Pin_FastInit</a> (provide specific values) or <a class="el" href="group__group__gpio__functions__init.html#gad61553f65d4e6bd827eb6464a7913461">Cy_GPIO_Pin_Init</a> (provide a filled <a class="el" href="structcy__stc__gpio__pin__config__t.html" title="This structure is used to initialize a single GPIO pin. ">cy_stc_gpio_pin_config_t</a> structure).</li>
<li>An entire port can be configured using <a class="el" href="group__group__gpio__functions__init.html#gaece2166923613cf7abb536d8a05bfd45">Cy_GPIO_Port_Init</a>. Provide a filled <a class="el" href="structcy__stc__gpio__prt__config__t.html" title="This structure is used to initialize a port of GPIO pins. ">cy_stc_gpio_prt_config_t</a> structure. The values in the structure are bitfields representing the desired value for each pin in the port.</li>
<li>Pin configuration and management is based on the port address and pin number. <a class="el" href="group__group__gpio__functions__init.html#gab0eeafea970eadb4e147ff6d0e3804dc">Cy_GPIO_PortToAddr</a> function can optionally be used to calculate the port address from the port number at run-time.</li>
<li>Each I/O is individually configurable to one of eight drive modes represented by drivemode of <a class="el" href="structcy__stc__gpio__pin__config__t.html" title="This structure is used to initialize a single GPIO pin. ">cy_stc_gpio_pin_config_t</a> structure.</li>
</ul>
<p>Once the pin/port initialization is complete, each pin can be accessed by specifying the port (<a class="el" href="struct_g_p_i_o___p_r_t___type.html" title="The struct type definition for the hardware register set contained in the block.  The address of a va...">GPIO_PRT_Type</a>) and the pin (0-7) in the provided API functions.</p>
<h1><a class="anchor" id="group_gpio_configuration"></a>
Configuration Considerations</h1>
<ol type="1">
<li>Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection. This allows the pin to connect to signal sources/sinks throughout the device, as defined by the pin HSIOM selection options (en_hsiom_sel_t).</li>
<li>All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW control digital pin only) at Power-On-Reset(POR).</li>
<li>Some API functions perform read-modify-write operations on shared port registers. These functions are not thread safe and care must be taken when called by the application.</li>
<li>Digital input buffer provides a high-impedance buffer for the external digital input. The input buffer is connected to the HSIOM for routing to the CPU port registers and selected peripheral. Enabling the input buffer provides possibility to read the pin state via the CPU. If pin is connected to an analog signal, the input buffer should be disabled to avoid crowbar currents. For more information refer to device TRM and the device datasheet.</li>
</ol>
<p>Multiple pins on a port can be updated using direct port register writes with an appropriate port mask. An example is shown below, highlighting the different ways of configuring Port 1 pins using:</p>
<ul>
<li>Initialize a Pin using <a class="el" href="structcy__stc__gpio__pin__config__t.html" title="This structure is used to initialize a single GPIO pin. ">cy_stc_gpio_pin_config_t</a> structure <div class="fragment"><div class="line"></div><div class="line">    <a class="code" href="structcy__stc__gpio__pin__config__t.html">cy_stc_gpio_pin_config_t</a> pinConfig = {</div><div class="line">        <span class="comment">/*.outVal =*/</span>       1UL,                    <span class="comment">/* Output = High */</span></div><div class="line">        <span class="comment">/*.driveMode =*/</span>    <a class="code" href="group__group__gpio__drive_modes.html#ga9e554ee7c43ac65a6d48274455b53823">CY_GPIO_DM_STRONG</a>,      <span class="comment">/* Resistive pull-up, input buffer on */</span></div><div class="line">        <span class="comment">/*.hsiom =*/</span>        P0_3_GPIO,              <span class="comment">/* Software controlled pin */</span></div><div class="line">        <span class="comment">/*.intEdge =*/</span>      <a class="code" href="group__group__gpio__interrupt_trigger.html#gafbaa3f5dff9b5689cdb43bb07c7c6fef">CY_GPIO_INTR_RISING</a>,    <span class="comment">/* Rising edge interrupt */</span></div><div class="line">        <span class="comment">/*.intMask =*/</span>      1UL,                    <span class="comment">/* Enable port interrupt for this pin */</span></div><div class="line">        <span class="comment">/*.vtrip =*/</span>        <a class="code" href="group__group__gpio__vtrip.html#ga0eb9d3f41338feae28103e8a8c302ba0">CY_GPIO_VTRIP_CMOS</a>,     <span class="comment">/* CMOS voltage trip */</span></div><div class="line">        <span class="comment">/*.slewRate =*/</span>     <a class="code" href="group__group__gpio__slew_rate.html#gabb43620358101afd1663376cb3ba19b4">CY_GPIO_SLEW_FAST</a>,      <span class="comment">/* Fast slew rate */</span></div><div class="line">        <span class="comment">/*.driveSel =*/</span>     <a class="code" href="group__group__gpio__drive_strength.html#ga203ca4e69600122e76e45dbaa2f013fb">CY_GPIO_DRIVE_FULL</a>,     <span class="comment">/* Full drive strength */</span></div><div class="line">        <span class="comment">/*.vregEn =*/</span>       0UL,                    <span class="comment">/* SIO-specific setting - ignored */</span></div><div class="line">        <span class="comment">/*.ibufMode =*/</span>     0UL,                    <span class="comment">/* SIO-specific setting - ignored */</span></div><div class="line">        <span class="comment">/*.vtripSel =*/</span>     0UL,                    <span class="comment">/* SIO-specific setting - ignored */</span></div><div class="line">        <span class="comment">/*.vrefSel =*/</span>      0UL,                    <span class="comment">/* SIO-specific setting - ignored */</span></div><div class="line">        <span class="comment">/*.vohSel =*/</span>       0UL                     <span class="comment">/* SIO-specific setting - ignored */</span></div><div class="line">    };</div><div class="line"></div><div class="line">    <span class="comment">/* Initialize pin P0.3 */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__enums.html#gga0ba12c6f18fa9e356ceea0218beb7259ac12fe3dac92e654617ce1a0cda34c0b0">CY_GPIO_SUCCESS</a> != <a class="code" href="group__group__gpio__functions__init.html#gad61553f65d4e6bd827eb6464a7913461">Cy_GPIO_Pin_Init</a>(P0_3_PORT, P0_3_NUM, &amp;pinConfig))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Insert error handling */</span></div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></li>
<li>Initialize entire port using <a class="el" href="structcy__stc__gpio__prt__config__t.html" title="This structure is used to initialize a port of GPIO pins. ">cy_stc_gpio_prt_config_t</a> structure <div class="fragment"><div class="line">    <span class="comment">/* Scenario: Initialize GPIO port 0:</span></div><div class="line"><span class="comment">     * - 3 pin as input with resistive pull-up and rising edge interrupt;</span></div><div class="line"><span class="comment">     * - 5 pin as output in a strong drive mode with initial state high. */</span></div><div class="line"><span class="preprocessor">    #define PIN_INPUT_NUM   3u</span></div><div class="line"><span class="preprocessor">    #define PIN_OUTPUT_NUM  5u</span></div><div class="line"></div><div class="line"><span class="preprocessor">    #define PIN_HIGH        1u</span></div><div class="line"><span class="preprocessor">    #define INTR_ENABLE     1u</span></div><div class="line"><span class="preprocessor">    #define INTR_CFG_LEN    2u</span></div><div class="line"><span class="preprocessor">    #define PIN_DM_CFG_LEN  4u</span></div><div class="line"></div><div class="line">    <a class="code" href="structcy__stc__gpio__prt__config__t.html">cy_stc_gpio_prt_config_t</a> portConfig = {</div><div class="line">        <span class="comment">/*.out        =*/</span> (PIN_HIGH &lt;&lt; PIN_OUTPUT_NUM),                                 <span class="comment">/* PX.5 output value = 1 */</span></div><div class="line">        <span class="comment">/*.intrMask   =*/</span> (INTR_ENABLE &lt;&lt; PIN_INPUT_NUM),                               <span class="comment">/* PX.3 interrupt enabled */</span></div><div class="line">        <span class="comment">/*.intrCfg    =*/</span> (<a class="code" href="group__group__gpio__interrupt_trigger.html#gafbaa3f5dff9b5689cdb43bb07c7c6fef">CY_GPIO_INTR_RISING</a> &lt;&lt; (PIN_INPUT_NUM * INTR_CFG_LEN)),      <span class="comment">/* PX.3 rising edge interrupt */</span></div><div class="line">        <span class="comment">/*.cfg        =*/</span> ((<a class="code" href="group__group__gpio__drive_modes.html#ga822f7d73072811b69a754d70806247b9">CY_GPIO_DM_PULLUP</a> &lt;&lt; (PIN_INPUT_NUM  * PIN_DM_CFG_LEN)) |   <span class="comment">/* PX.3 resistive pull-up */</span></div><div class="line">                          (<a class="code" href="group__group__gpio__drive_modes.html#ga9e554ee7c43ac65a6d48274455b53823">CY_GPIO_DM_STRONG</a> &lt;&lt; (PIN_OUTPUT_NUM  * PIN_DM_CFG_LEN))),   <span class="comment">/* PX.5 strong drive */</span></div><div class="line">        <span class="comment">/*.cfgIn      =*/</span> 0x00000000u,                                                  <span class="comment">/* PX[7:0] CMOS trip (default value)*/</span></div><div class="line">        <span class="comment">/*.cfgOut     =*/</span> 0x00000000u,                                                  <span class="comment">/* PX[7:0] Fast slew rate, full drive strength (default value) */</span></div><div class="line">        <span class="comment">/*.cfgSIO     =*/</span> 0x00000000u,                                                  <span class="comment">/* PX[7:0] ignored (default value) */</span></div><div class="line">        <span class="comment">/*.sel0Active =*/</span> 0x00000000u,                                                  <span class="comment">/* PX[3:0] Use GPIO HSIOM (default value) */</span></div><div class="line">        <span class="comment">/*.sel1Active =*/</span> 0x00000000u,                                                  <span class="comment">/* PX[7:4] Use GPIO HSIOM (default value) */</span></div><div class="line">    };</div><div class="line"></div><div class="line">    <span class="comment">/* Initialize GPIO port 0 */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__enums.html#gga0ba12c6f18fa9e356ceea0218beb7259ac12fe3dac92e654617ce1a0cda34c0b0">CY_GPIO_SUCCESS</a> != <a class="code" href="group__group__gpio__functions__init.html#gaece2166923613cf7abb536d8a05bfd45">Cy_GPIO_Port_Init</a>(GPIO_PRT0, &amp;portConfig))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Insert error handling */</span></div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></li>
<li>Port output data register</li>
<li>Port output data set register</li>
<li>Port output data clear register</li>
</ul>
<div class="fragment"><div class="line">    <a class="code" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a>* portAddr;</div><div class="line">    uint8_t value;</div><div class="line"></div><div class="line">    <span class="comment">/* Set the port address */</span></div><div class="line">    portAddr = GPIO_PRT1;</div><div class="line"></div><div class="line">    <span class="comment">/* Set the drive mode to STRONG for pins P1[0], P1[2] and P1[3] (other pins in this port are HIGHZ) */</span></div><div class="line">    CY_SET_REG32(&amp;portAddr-&gt;CFG, <a class="code" href="group__group__gpio__drive_modes.html#gacebd8bea6222d742bdfbfd86dabab940">CY_GPIO_DM_STRONG_IN_OFF</a> &lt;&lt; GPIO_PRT_CFG_DRIVE_MODE0_Pos |</div><div class="line">                                 <a class="code" href="group__group__gpio__drive_modes.html#gacebd8bea6222d742bdfbfd86dabab940">CY_GPIO_DM_STRONG_IN_OFF</a> &lt;&lt; GPIO_PRT_CFG_DRIVE_MODE2_Pos |</div><div class="line">                                 <a class="code" href="group__group__gpio__drive_modes.html#gacebd8bea6222d742bdfbfd86dabab940">CY_GPIO_DM_STRONG_IN_OFF</a> &lt;&lt; GPIO_PRT_CFG_DRIVE_MODE3_Pos );</div><div class="line"></div><div class="line">    <span class="comment">/* Set the pins P1[0], P1[2] and P1[3] to high and other pins in this port to low */</span></div><div class="line">    CY_SET_REG32(&amp;portAddr-&gt;OUT, GPIO_PRT_OUT_OUT0_Msk |</div><div class="line">                                 GPIO_PRT_OUT_OUT2_Msk |</div><div class="line">                                 GPIO_PRT_OUT_OUT3_Msk);</div><div class="line"></div><div class="line">    <span class="comment">/* Set the pins P1[2] and P1[3] to low (other pins in this port are unchanged) */</span></div><div class="line">    CY_SET_REG32(&amp;portAddr-&gt;OUT_CLR, GPIO_PRT_OUT_CLR_OUT2_Msk |</div><div class="line">                                     GPIO_PRT_OUT_CLR_OUT3_Msk);</div><div class="line"></div><div class="line">    <span class="comment">/* Set the pin P1[3] to high again (other pins in this port are unchanged) */</span></div><div class="line">    CY_SET_REG32(&amp;portAddr-&gt;OUT_SET, GPIO_PRT_OUT_SET_OUT3_Msk);</div><div class="line"></div><div class="line">    <span class="comment">/* Read the port data (value should be 0b00001001) */</span></div><div class="line">    value = CY_GET_REG32(&amp;portAddr-&gt;OUT);</div><div class="line"></div><div class="line">    <span class="comment">/* Set pin P1[3] to low (other pins are not impacted) */</span></div><div class="line">    CY_SET_REG32(&amp;portAddr-&gt;OUT, _CLR_SET_FLD32U(portAddr-&gt;OUT, GPIO_PRT_OUT_OUT3, 0u));</div><div class="line"></div><div class="line">    <span class="comment">/* Set pin P1[2] to high (other pins are not impacted) */</span></div><div class="line">    CY_SET_REG32(&amp;portAddr-&gt;OUT, _CLR_SET_FLD32U(portAddr-&gt;OUT, GPIO_PRT_OUT_OUT2, 1u));</div></div><!-- fragment --> <h1><a class="anchor" id="group_gpio_more_information"></a>
More Information</h1>
<p>Refer to the technical reference manual (TRM) and the device datasheet.</p>
<h1><a class="anchor" id="group_gpio_changelog"></a>
Changelog</h1>
<table class="doxtable">
<tr>
<th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
<tr>
<td>1.140 </td><td>Updated APIs <a class="el" href="group__group__gpio__functions__init.html#gaece2166923613cf7abb536d8a05bfd45">Cy_GPIO_Port_Init</a>, <a class="el" href="group__group__gpio__functions__gpio.html#gaaac989df7f0158c5b6549c86e5034479">Cy_GPIO_WritePort</a>. </td><td>Defect fix.  </td></tr>
<tr>
<td>1.130 </td><td>Added new APIs to support new devices (particularly Traveo II Cluster) with Drive Trim features: <a class="el" href="group__group__gpio__functions__gpio.html#gae7942739fe1e69b5d38f7e2437d135bc">Cy_GPIO_SetDriveSelTrim</a>, <a class="el" href="group__group__gpio__functions__gpio.html#gad1af3b2d1ec5b218d30c355be3a42ed4">Cy_GPIO_GetDriveSelTrim</a>. </td><td>New functionality.  </td></tr>
<tr>
<td rowspan="2">1.120 </td><td>Added new APIs: <a class="el" href="group__group__gpio__functions__gpio.html#gaaac989df7f0158c5b6549c86e5034479">Cy_GPIO_WritePort</a>. </td><td>New functionality.  </td></tr>
<tr>
<td>Reworked API structure to support new devices. </td><td>Code enhancement.  </td></tr>
<tr>
<td>1.110 </td><td>Added support for SMIF GPIO PORT1 and PORT2 and reverted to GPIO inline functions. </td><td>Code enhancement and support for new GPIO port for SMIF.  </td></tr>
<tr>
<td>1.100 </td><td>Added support for TRAVEO&trade; II Body Entry devices.<br />
 Updated pre-processor checks to check for GPIO auto-leveling capability rather than rely on IOSS version. </td><td>Code enhancement and support for new devices.  </td></tr>
<tr>
<td>1.90 </td><td>Updated APIs <a class="el" href="group__group__gpio__functions__init.html#gaece2166923613cf7abb536d8a05bfd45">Cy_GPIO_Port_Init</a>, <a class="el" href="group__group__gpio__functions__init.html#gad996e3e1fc44d28611e9b83fc025994b">Cy_GPIO_Port_Deinit</a>, <a class="el" href="group__group__gpio__functions__gpio.html#gaedda162438c80e6455f47a738a5d391a">Cy_GPIO_GetDrivemode</a>. </td><td>Fixed coverity defects.  </td></tr>
<tr>
<td rowspan="2">1.80 </td><td>Updated <a class="el" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a> and <a class="el" href="group__group__gpio__functions__gpio.html#gaedda162438c80e6455f47a738a5d391a">Cy_GPIO_GetDrivemode</a> APIs. </td><td>Updated drive mode configuration for CAT1D devices.  </td></tr>
<tr>
<td>Fixed MISRA 2012 violations. </td><td>MISRA 2012 compliance.  </td></tr>
<tr>
<td>1.70 </td><td>Updated driver to support the CAT1D family of devices. </td><td>Added new family of devices.  </td></tr>
<tr>
<td rowspan="2">1.60 </td><td>Added <a class="el" href="group__group__gpio__functions__gpio.html#ga877ae84c544a65ea19347dae57652d48">Cy_GPIO_SetVtripAuto</a> and <a class="el" href="group__group__gpio__functions__gpio.html#ga85ac7b2dd2bd7902a5c39ab43eb1211b">Cy_GPIO_GetVtripAuto</a> APIs for configuring GPIO input buffer voltage for automotive compatible or not, for CAT1C devices. </td><td>New APIs support for CAT1C devices.  </td></tr>
<tr>
<td>Fixed unused variables error. </td><td>Minor error fixes.  </td></tr>
<tr>
<td>1.50.1 </td><td>Updated doxygen for External clock source to HF0. </td><td>Documentation enhancement.  </td></tr>
<tr>
<td>1.50 </td><td>Modified <a class="el" href="group__group__gpio__functions__init.html#gad61553f65d4e6bd827eb6464a7913461">Cy_GPIO_Pin_Init</a>, <a class="el" href="group__group__gpio__functions__init.html#gaf57c501727276013d3e8974a9fb7d0a7">Cy_GPIO_Pin_FastInit</a>, and <a class="el" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a> APIs to catch wrong drive modes. </td><td>Defect fix.  </td></tr>
<tr>
<td rowspan="2">1.40 </td><td>Changes in Support of the new family of devices </td><td>Added new family of devices  </td></tr>
<tr>
<td>Changes in support of Secure pins used for External clocks on Secure devices </td><td>Added support for accessing External clocks protected pins  </td></tr>
<tr>
<td>1.30 </td><td>Fixed/documented MISRA 2012 violations. </td><td>MISRA 2012 compliance.  </td></tr>
<tr>
<td>1.20.1 </td><td>Minor documentation updates. </td><td>Documentation enhancement.  </td></tr>
<tr>
<td rowspan="3">1.20 </td><td>Flattened the organization of the driver source code into the single source directory and the single include directory. </td><td>Driver library directory-structure simplification.  </td></tr>
<tr>
<td>Added the functions for configuring the AMux bus splitter switch cells:<ul>
<li><a class="el" href="group__group__gpio__functions__gpio.html#ga8d7972a161fe097a01a55f9cd31b1f03">Cy_GPIO_SetAmuxSplit</a></li>
<li><a class="el" href="group__group__gpio__functions__gpio.html#ga52c69476c1755f4d60b491862f10f68c">Cy_GPIO_GetAmuxSplit</a>  </li>
</ul>
</td><td>Added a new functionality related to AMux bus.  </td></tr>
<tr>
<td>Added register access layer. Use register access macros instead of direct register access using dereferenced pointers. </td><td>Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.  </td></tr>
<tr>
<td>1.10.1 </td><td><p class="starttd">Updated description for the functions: <a class="el" href="group__group__gpio__functions__interrupt.html#ga4d9dc7505ab3ceaa67b8aa8188dfbbcc">Cy_GPIO_GetInterruptStatus</a>, <a class="el" href="group__group__gpio__functions__interrupt.html#ga2ce3c22693c93b7fce2e3025211b0d28">Cy_GPIO_GetInterruptMask</a>, <a class="el" href="group__group__gpio__functions__interrupt.html#ga0fe3520611b491618e21322ab441343d">Cy_GPIO_GetInterruptStatusMasked</a>.</p>
<p class="endtd">Minor documentation edits.  </p>
</td><td>Documentation update and clarification  </td></tr>
<tr>
<td>1.10 </td><td>Added input parameter validation to the API functions </td><td></td></tr>
<tr>
<td>1.0 </td><td>Initial version </td><td></td></tr>
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